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1 tm march 1997 hd-15531 cmos manchester encoder-decoder features ? support of mil-std-1553 ? data rate (15531b) . . . . . . . . . . . . . . . .2.5 megabit/sec ? data rate (15531) . . . . . . . . . . . . . . . . .1.25 megabit/sec ? variable frame length to 32 bits ? sync identification and lock-in ? separate manchester ii encode, decode ? low operating power . . . . . . . . . . . . . . . . . 50mw at 5v ordering information description the intersil hd-15531 is a high performance cmos device intended to service the requirements of mil-std-1553 and similar manchester ii encoded, time division multiplexed serial data protocols. this lsi chip is divided into two sec- tions, an encoder and a decoder. these sections operate independently of each other, except for the master reset and word length functions. this circuit provides many of the requirements of mil-std-1553. the encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. the decoder recognizes the sync pulse and identi- fies it as well as decoding the data bits and checking parity. the hd-15531 also surpasses the requirements of mil- std-1553 by allowing the word length to be programmable (from 2 to 28 data bits). a frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. this chip also allows selection of either even or odd parity for the encoder and decoder separately. this integrated circuit is fully guaranteed to support the 1mhz data rate of mil-std-1553 over both temperature and voltage. for high speed applications the 15531b will support a 2.5 megabit/sec data rate. the hd-15531 can also be used in many party line digital data communications applications, such as a local area net- work or an environmental control system driven from a single twisted pair of fiber optic cable throughout a building. package temp. range ( o c) 1.25mbit /sec 2.5mbit /sec pkg. no. pdip -40 to 85 - hd3-15531b-9 e40.6 cerdip -40 to 85 HD1-15531-9 HD1-15531b-9 f40.6 -55 to 125 HD1-15531-8 HD1-15531b-8 f40.6 desc (cerdip) -55 to 125 5962- 9054901mqa HD1-15531 f40.6 -55 to 125 5962- 9054902mqa HD1-15531b f40.6 fn2961.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 pinout hd-15531 (cerdip, pdip) top view block diagrams endoder 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 take data? v cc valid word take data serial data out synchr data synchr data sel synchr clk bipolar zero in bipolar one in unipolar data in decoder shift clk synchr clk sel decoder clk transition sel nc command sync decoder parity sel decoder reset count c 0 33 34 35 36 37 38 39 40 32 31 30 29 24 25 26 27 28 21 22 23 count c 1 data sync encoder clk count c 4 nc encoder shift clk send clk in send data encoder parity sel sync sel encoder enable serial data in count c2 master reset gnd count c 3 6 out bipolar one out bipolar zero out output inhibit 2 6 v cc 25 27 32 bipolar one out bipolar zero out sync select encoder enable encoder shift clk send data serial data in 34 28 29 31 encoder clk 37 gnd master reset send clk in 21 22 33 24 6 out 1 26 output inhibit 30 character bit counter encoder parity select 20 40 23 36 39 c 0 c 1 c 2 c 3 c 4 former hd-15531
3 decoder pin description pin number type name section description 1v cc both positive supply pin. a 0.1 f decoupling capacitor from v cc (pin 1) to ground (pin 21) is recommended. 2 o valid word decoder output high indicates receipt of a valid word, (valid parity and no manchester errors). 3 o take data? decoder a continuous, free running signal provided for host timing or data handling. when data is present on the bus, this signal will be synchronized to the incoming data and will be identical to take data. 4 o take data decoder output is high during receipt of data after identification of a valid sync pulse and two valid manchester bits. 5 o serial data out decoder delivers received data in correct nrz format. 6 i synchronous data decoder input presents manchester data directly to character identification logic. synchronous data select must be held high to use this input. if not used, this pin must be held high. 7 i synchronous data select decoder in high state allows the synchronous data to enter the character identification logic. tie this input low for asynchronous data. 8 i synchronous clock decoder input provides externally synchronized clock to the decoder, for use when re- ceiving synchronous data. this input must be tied high when not in use. 9 i decoder clock decoder input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the decoder. input a frequency equal to 12x the data rate. 10 i synchronous clock selct decoder in high state directs the synchronous clock to control the decoder char- acter identification logic. a low state selects the decoder clock. 11 i bipolar zero in decoder a high input should be applied when the bus is in its negative state. this pin must be held high when the unipolar input is used. 12 i bipolar one in decoder a high input should be applied when the bus is in its positive state. this pin must he held low when the unipolar input is used. 13 i unipolar data in decoder with pin 11 high and pin 12 low, this pin enters unipolar data into the transition finder circuit. if not used this input must be held low. bipolar one in bipolar decoder master 13 12 11 9 15 synchronizer 8 10 22 decoder synchronous synchronous decoder valid word serial take data command sync data sync 4 17 5 2 16 19 decoder reset 14 3 take data? parity 20 40 23 36 39 bit counter clock 7 8 synchronous synchronous c 0 c 1 c 2 c 3 c 4 transition finder data select gate parity character identifier bit unipolar data in one in clk clk select clk clk select reset data out select shift clk check rate clk select data data data select hd-15531
4 14 o decoder shift clock decoder output which delivers a frequency (decoder clock + 1 2), synchronous by the recovered serial data stream. 15 i transition se- lect decoder a high input to this pin causes the transition finder to synchronize on every tran- sition of input data. a low input causes the transition finder to synchronize only on mid-bit transitions. 16 nc blank not connected. 17 o command sync decoder output of a high from this pin occurs during output of decoded data which was preceded by a command (or status) synchronizing character. 18 i decoder parity select decoder an input for parity sense, calling for even parity with input high and odd parity with input low. 19 i decoder reset decoder a high input to this pin during a rising edge of decoder shift clock resets the decoder bit counting logic to a condition ready for a new word. 20 i count c0 both one of five binary inputs which establish the total bit count to be encoded or de- coded. 21 ground both supply pin. 22 i master reset both a high on this pin clears 2:1 counters in both encoder and decoder, and resets the 6 circuit. 23 i count c2 both see pin 20. 24 o 6 out encoder output from 6:1 divider which is driven by the encoder clock. 25 o bipolar zero out encoder an active low output designed to drive the zero or negative sense of a bipolar line driver. 26 i output inhibit encoder a low on this pin forces pin 25 and 27 high, the inactive states. 27 o bipolar one out encoder an active low output designed to drive the one or positive sense of a bipolar line driver. 28 i serial data in encoder accepts a serial data stream at a data rate equal to encoder shift clock. 29 i encoder enable encoder a high on this pin initiates the encode cycle. (subject to the preceding cycle be- ing complete). 30 i sync select encoder actuates a command sync for an input high and data sync for an input low. 31 i encoder parity select encoder sets transmit parity odd for a high input, even for a low input. 32 o send data encoder is an active high output which enables the external source of serial data. 33 i send clock in encoder clock input at a frequency equal to the data rate x2, usually driven by 6 output. 34 o encoder shift clock encoder output for shifting data into the encoder. the encoder samples sdi pin-28 on the low-to-high transition of esc. 35 nc blank not connected. 36 i count c3 both see pin 20. 37 i encoder clock encoder input to the 6:1 divider, a frequency equal to 12 times the data rate is usually input here. 38 o data sync decoder output of a high from this pin occurs during output of decoded data which was preceded by a data synchronizing character. 39 i count c4 both see pin 20. 40 i count c1 both see pill 20. pin description (continued) pin number type name section description hd-15531
5 encoder operation the encoder requires a single clock with a frequency of twice the desired data rate applied at the send clock input. an auxiliary divide by six counter is provided on chip which can be utilized to produce the send clock by divid- ing the decoder clock. the frame length is set by pro- gramming the count inputs. parity is selected by programming encoder parity select high for odd par- ity or low for even parity. the encoder?s cycle begins when encoder enable is high during a falling edge of encoder shift clock . this cycle lasts for one word length or k + 4 encoder shift clock periods, where k is the number of bits to be sent. at the next low-to-high transition of the encoder shift clock, a high sync select input actuates a command sync or a low will produce a data sync for the word . when the encoder is ready to accept data, the send data output will go high for k encoder shift clock periods . during these k periods the data should be clocked into the serial data input with every high-to- low transition of the encoder shift clock - so it can be sampled on the low-to-high transition. after the sync and manchester ii encoded data are transmitted through the bipolar one and bipolar zero outputs, the encoder adds on an additional bit with the parity for that word . if encoder enable is held high continuously, consecutive words will be encoded without an interframe gap. encoder enable must go low by time (as shown) to prevent a consecutive word from being encoded. at any time a low on output inhibit input will force both bipolar out- puts to a high state but will not affect the encoder in any other way. to abort the encoder transmission, a positive pulse must be applied at master reset. any time after or during this pulse, a low-to-high transition on send clock clears the internal counters and initializes the encoder for a new word. decoder operation to operate the decoder asynchronously requires a single clock with a frequency of 12 times the desired data rate applied at the decoder clock input. to operate the decoder synchronously requires a synchronous clock at a frequency 2 times the data rate which is syn- chronized with the data at every high-to-low transition applied to the synchronous clk input. the manchester ii coded data can be presented to the decoder asynchro- nously in one of two ways. the bipolar one and bipolar zero inputs will accept data from a comparator sensed transformer coupled bus as specified in military spec 1553. the unipolar data input can only accept nonin- verted manchester ii coded data. (e.g., from bipolar one out on an encoder through an inverter to unipolar data input). the decoder is free running and continuously monitors its data input lines for a valid sync character and two valid manchester data bits to start an output cycle. when a valid sync is recognized , the type of sync is indicated by a high level at either command sync or data sync output. if the sync character was a command sync the command sync output will go high and remain high for k shift clock periods , where k is the number of bits to be received. if the sync character was a data sync, the data sync output will go high. the take data output will go high and remain high - while the decoder is transmit- 1 2 4 3 4 5 5 figure 1. encoder send clock bit k-1 bit k-3 bit k-4 bit k-5 bit 4 bit k-2 msb bit 3 bit 2 bit 1 parity bit 1 bit 2 bit 3 bit 4 bit 4 bit 3 bit 2 bit 1 parity 1st half 2nd half msb bit k-1 bit k-2 bit k-3 bit k-4 sync sync msb bit k-1 4 5 3 2 1 valid timing 0 1 2 3 4 5 6 7 n-3 n-2 n-1 n n-4 encoder shift clock encoder enable sync select send data serial data in bipolar one out bipolar zero out don?t care don?t care bit k-2 bit k-3 bit k-4 1 2 3 2 3 hd-15531
6 ting the decoded data through serial data out. the decoded data available at serial data out is in nrz format. the decoder shift clock is provided so that the decoded bits can get shifted into an external register on every low-to-high transition of this clock - . note that decoder shift clock may adjust its phase up until the time that take data goes high. after all k decoded bits have been transmitted the data is checked for parity. a high input on decoder parity select will set the decoder to check for even parity or a low input will set the decoder to check for odd parity. a high on valid word output indicates a successful reception of a word without any manchester or parity errors. at this time the decoder is looking for a new sync character to start another output sequence. valid word will go low approx- imately k + 4 decoder shift clock periods after it goes high, if not reset low sooner by a valid sync and two valid manchester bits as shown . at any time in the above sequence a high input on decoder reset during a low-to-high transition of decoder shift clock will abort transmission and ini- tialize the decoder to start looking for a new sync character. 2 3 3 4 1 serial 1st half timing synchronous clock decoder shift clock bipolar one in bipolar zero in take data 2nd half sync sync msb msb bit k-1 bit k-1 bit k-2 bit k-2 bit k-3 bit k-3 bit k-5 bit k-4 bit k-5 bit k-4 012345678 n-3n-2n-1n bit 3 bit 2 parity bit 1 bit 2 bit 3 bit 1 parity bitk-1 valid word data sync command msb bitk-2 bitk-3 bit 5 bit 4 bit 3 bit 2 bit 1 3 4 2 1 (may be high from previous reception) undefined data out sync figure 2. decoder hd-15531
7 frame counter data bits frame length (bit periods) pin word c 4 c 3 c 2 c 1 c 0 26llhlh 37llhhl 4 8 l l hhh 5 9 lhlll 610lhllh 711lhlhl 812lhlhh 913lhhll 10 14 l h h l h 11 15 l h h h l 12 16 l hhhh 13 17 h l l l l 14 18 h l l l h 15 19 h l l h l 16 20 h l l h h 17 21 h l h l l 18 22 h l h l h 19 23 h l h h l 20 24 h l h h h 21 25 h h l l l 22 26 h h l l h 23 27 h h l h l 24 28 h h l h h 25 29 h h h l l 26 30 h h h l h 27 31 h h h h l 28 32 hhhhh note: 1. the above table demonstrates all possible combinations of frame lengths ranging from 6 to 32 bits. the pin word described her e is com- mon to both the encoder and decoder. hd-15531
8 typical timing diagrams for a manchester encoded uart v cc sh/ld si 74165 74165 parallel in o h ck sh/ld ck parallel out master reset 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 40 39 38 37 36 35 34 33 32 31 30 29 21 22 23 24 25 26 27 28 count c 0 decoder parity select command sync transition select unipolar data in bipolar one in bipolar zero in sync clock select decoder clock sync clock sync data select count c 4 count c 1 count c 3 count c 2 bipolar zero out inhibit output bipolar one out encoder enable sync select encoder parity sel. nc si nc ab ckh ab ck 74164 74164 o h data sync sync data take data valid word figure 3. how to make our mtu look like a manchester encoded uart valid encoder enable sync select parallel in bipolar one out bipolar zero out valid lsb p sync msb parity p figure 4. encoder timing hd-15531
9 mil-std-1553 the 1553 standard defines a time division multiplexed data bus for application within aircraft. the bus is defined to be bipolar, and encoded in a manchester ii format, so no dc component appears on the bus. this allows transformer cou- pling and excellent isolation among systems and their envi- ronment. the hd-15531 supports the full bipolar configuration, assuming a bus driver configuration similar to that in figure 1. bipolar inputs from the bus, like figure 2, are also accommodated. the signaling format in mil-std-1553 is specified on the assumption that the network of 32 or fewer terminals are controlled by a central control unit by means of command- words, and data. terminals respond with status words, and data. each word is preceded by a synchronizing pulse, and followed by parity bit, occupying a total of 20 s. the word formats are shown in figure 4. the special abbreviations are as follows: p parity, which is defined to be odd, taken across all 17 bits. r/t receive on logical zero, transmit on one. me message error if logical 1. tf terminal flag, if set, calls for controller to request self-test data. bipolar one in bipolar zero in lsb p sync msb parity p command sync valid word parallel out valid valid from previous reception figure 5. decoder timing figure 6. simplified mil-std-1553 driver figure 7. simplified mil-std-1553 receiver ?0 ? ?1 ? bus + - + - ?1 ? ?0 ? ?1? ref ?0? ref hd-15531
10 figure 8. mil-std-1553 character formats figure 9. mil-std-1553 word formats note: 1. this page is a summary of mil-std-1553 and is not intended to describe the operation of the hd-15531. bit period bit period bit period logical one data logical zero data command sync data sync terminal sync 0 1 2 3 4 5 6 7 8 9 101112131415161718 19 command word (from controller to terminal) data word (sent either direction) status word (from terminal to controller) 51 5 5 1 p address sub address /mode data word count sync r/t data word 1 p 51 9 1 1 terminal address code for failure modes p sync tf 16 hd-15531
11 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range (t a ) hd-15531-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c hd-15531-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c encoder/decoder clock rise time (tecr, tdcr) . . . . . . . 8ns max encoder/decoder clock fall time (tecf, tdcf) . . . . . . . . 8ns max thermal resistance (typical) ja jc cerdip package . . . . . . . . . . . . . . . . . . 35 o c/w 9 o c/w pdip package . . . . . . . . . . . . . . . . . . . . . 50 o c/w n/a storage temperature range . . . . . . . . . . . . . . . . .-65 o c to +150 o c maximum junction temperature ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c maximum lead temperature (soldering 10s). . . . . . . . . . . . +300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 gates sync. transition span (td2). . . . . . . . . . . 18 tdc typical, (note 1) short data transition span (td4). . . . . . . . 6 tdc typical, (note 1) long data transition span (td5) . . . . . . . 12 tdc typical, (note 1) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. dc electrical specifications v cc = 5.0v 10%, t a = -40 o c to +85c o (hd-15531-9) t a = -55 o c to +125c o (hd-15531-8) parameter symbol test conditions min max units input low voltage v il v cc = 4.5v and 5.5v - 0.2 v cc v input high voltage v ih v cc = 4.5v and 5.5v 0.7 v cc -v input low clock voltage v ilc v cc = 4.5v and 5.5v - gnd +0.5 v input high clock voltage v ihc v cc = 4.5v and 5.5v v cc -0.5 - v output low voltage v ol i ol = +1.8ma, v cc = 4.5v (note 2) - 0.4 v output high voltage v oh i oh = -3.0ma, v cc = 4.5v (note 2) 2.4 - v input leakage current i i v i = v cc or gnd, v cc = 5.5v -1.0 +1.0 a standby supply current i ccsb v in = v cc = 5.5v, outputs open -2ma operating power supply current iccop v in = v cc = 5.5v, f = 15mhz, outputs open -10ma functional test f t (note 3) - - - notes: 1. tdc = decoder clock period = 1/fdc. 2. interchanging of force and sense conditions is permitted. 3. tested as follows: f = 15mhz, v ih = 70% v cc , v il = 20% v cc , c l = 50pf, v oh v cc /2 and v ol v cc /2. capacitance t a = +25 o c, frequency = 1mhz symbol parameter typ units test conditions c in input capacitance 25 pf all measurements are referenced to device gnd c out output capacitance 25 pf hd-15531
12 ac electrical specifications v cc = 5v 10%, t a = -40 o c to +85 o c (hd-15530-9) t a = -55 o c to +125 o c (hd-15530-8) symbol parameter hd-15531 hd-15531b units test conditions (note 2) min max min max encoder timing fec encoder clock frequency - 15 - 30 mhz v cc = 4.5v and 5.5v, c l = 50pf fesc send clock frequency - 2.5 - 5.0 mhz v cc = 4.5v and 5.5v, c l = 50pf fed encoder data rate - 1.25 - 2.5 mhz v cc = 4.5v and 5.5v, c l = 50pf tmr master reset pulse width 150 - 150 - ns v cc = 4.5v and 5.5v, c l = 50pf te1 shift clock delay - 125 - 80 ns v cc = 4.5v and 5.5v, c l = 50pf te2 serial data setup 75 - 50 - ns v cc = 4.5v and 5.5v, c l = 50pf te3 serial data hold 75 - 50 - ns v cc = 4.5v and 5.5v, c l = 50pf te4 enable setup 90 - 90 - ns v cc = 4.5v and 5.5v, c l = 50pf te5 enable pulse width 100 - 100 - ns v cc = 4.5v and 5.5v, c l = 50pf te6 sync setup 55 - 55 - ns v cc = 4.5v and 5.5v, c l = 50pf te7 sync pulse width 150 - 150 - ns v cc = 4.5v and 5.5v, c l = 50pf te8 send data delay 0 50 0 50 ns v cc = 4.5v and 5.5v, c l = 50pf te9 bipolar output delay - 130 - 130 ns v cc = 4.5v and 5.5v, c l = 50pf te10 enable hold 10 - 10 - ns v cc = 4.5v and 5.5v, c l = 50pf te11 sync hold 95 - 95 - ns v cc = 4.5v and 5.5v, c l = 50pf decoder timing fdc decoder clock frequency - 15 - 30 mhz v cc = 4.5v and 5.5v, c l = 50pf fds decoder sync clock - 2.5 - 5.0 mhz v cc = 4.5v and 5.5v, c l = 50pf fdd decoder data rate - 1.25 - 2.5 mhz v cc = 4.5v and 5.5v, c l = 50pf tdr decoder reset pulse width 150 - 150 - ns v cc = 4.5v and 5.5v, c l = 50pf tdrs decoder reset setup time 75 - 75 - ns v cc = 4.5v and 5.5v, c l = 50pf tdrh decoder reset hold time 10 - 10 - ns v cc = 4.5v and 5.5v, c l = 50pf tmr master reset pulse 150 - 150 - ns v cc = 4.5v and 5.5v, c l = 50pf td1 bipolar data pulse width tdc + 10 (note 1) - tdc + 10 (note 1) -nsv cc = 4.5v and 5.5v, c l = 50pf td3 one zero overlap - tdc - 10 (note 1) - tdc - 10 (note 1) ns v cc = 4.5v and 5.5v, c l = 50pf td6 sync delay (on) -20 110 -20 110 ns v cc = 4.5v and 5.5v, c l = 50pf td7 take data delay (on) 0 110 0 110 ns v cc = 4.5v and 5.5v, c l = 50pf td8 serial data out delay - 80 - 80 ns v cc = 4.5v and 5.5v, c l = 50pf td9 sync delay (off) 0 110 0 110 ns v cc = 4.5v and 5.5v, c l = 50pf td10 take data delay (off) 0 110 0 110 ns v cc = 4.5v and 5.5v, c l = 50pf td11 valid word delay 0 110 0 110 ns v cc = 4.5v and 5.5v, c l = 50pf td12 sync clock to shift clock delay -75-75nsv cc = 4.5v and 5.5v, c l = 50pf td13 sync data setup 75 - 75 - ns v cc = 4.5v and 5.5v, c l = 50pf notes: 1. tdc = decoder clock period = 1/fdc. 2. ac testing as follows: input levels: v ih = 70% v cc , v il = 20% v cc ; input rise/fall times driven at 1ns/v; timing reference levels: v cc /2; output load: c l = 50pf. hd-15531
13 timing waveforms figure 10. encoder timing send clock t e1 t e2 t e3 valid encoder shift clock serial data in send clock encoder shift clock encoder enable encoder shift clock sync select send data send clock bipolar one out or bipolar zero out valid t e1 t e10 t e4 t e11 t e5 t e6 valid t e7 t e8 t e9 hd-15531
14 figure 11. decoder timing timing waveforms (continued) data sync bit period bit period bit period t d2 command sync t d2 t d3 t d3 t d2 t d4 one one zero t d1 t d1 t d1 t d3 t d3 t d1 t d1 t d1 t d3 t d3 t d3 t d3 t d1 t d4 t d5 t d5 t d2 t d2 command sync t d2 t d2 t d4 t d5 t d5 t d4 t d4 zero one one one data sync boi bzi boi bzi boi bzi ui ui ui t d3 note: unipolar in = 0, for next diagrams. note: bipolar one in = 0, bipolar zero in = 1, for next diagrams. t d2 t d2 hd-15531
15 figure 12. decoder timings timing waveforms (continued) take data t d6 t d7 t d8 data bit t d9 t d10 t d10 t d11 t drs t dr t drh decoder shift clock command/data sync serial data out decoder shift clock command/data sync take data valid word decoder shift clock decoder reset decoder shift clock t d12 t d13 t d13 t d13 t d13 synchronous decoder shift synchronous input (with external bit synchronization) clock in clock synchronous clock in synchronous data in manchester phases hd-15531
16 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 test load circuit note: 1. includes stray and jig capacitance. a c testing input, output waveform note: 1. ac testing: all input signals must switch between v il and v ih , input rise and fall times are driven at 1ns per volt. dut c l (note 1) figure 13. input 50% 50% output v ol v oh v ih v il figure 14. hd-15531

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